# Intel Alder Lake P-core aka Golden Cove

References:

- [Popping the Hood on Golden Cove](<https://chipsandcheese.com/2021/12/02/popping-the-hood-on-golden-cove/>)
- [Intel Alder Lake CPU Architectures](<https://ieeexplore.ieee.org/document/9747991>)
- [Golden Cove](<https://en.wikipedia.org/wiki/Golden_Cove>)
- [Golden Cove’s Vector Register File: Checking with Official (SPR) Data](<https://chipsandcheese.com/2023/01/15/golden-coves-vector-register-file-checking-with-official-spr-data/>)
- [4th Gen Intel Xeon Scalable Sapphire Rapids Leaps Forward](<https://www.servethehome.com/4th-gen-intel-xeon-scalable-sapphire-rapids-leaps-forward/7/>)
- [Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs](<https://fuse.wikichip.org/news/6111/intel-details-golden-cove-next-generation-big-core-for-client-and-server-socs/>)
- [Sapphire Rapids: Golden Cove Hits Servers](<https://chipsandcheese.com/2023/03/12/a-peek-at-sapphire-rapids/>)
- [Golden Cove’s Lopsided Vector Register File](<https://chipsandcheese.com/2022/12/25/golden-coves-lopsided-vector-register-file/>)
- [Alder Lake Architecture on Hot Chips 33](<https://hc33.hotchips.org/assets/program/conference/day1/HC2021.C1.1 Intel Efraim Rotem.pdf>)
- [Sapphire Rapids on Hot Chips 33](<https://hc33.hotchips.org/assets/program/conference/day1/HC2021.C1.4 Intel Arijit.pdf>)
- Intel 64 and IA-32 Architectures Optimization Reference Manual Volume 1
- [Sapphire Rapids Dieshot](<https://www.bilibili.com/video/BV1nb421J7jy/>)