__lasx_xvilvl_d

LASX intrinsic · group: Misc

Synopsis

__m256i __lasx_xvilvl_d (__m256i a, __m256i b)
#include <lasxintrin.h>
Instruction: xvilvl.d xr, xr, xr
CPU Flags: LASX

Description

For each 128-bit lane, interleave the 64-bit elements in the lower half of that lane from a and b: the element from b is placed at the even output position and the element from a at the following odd position.

Operation

int i;
for (i = 0; i < 2; i++) {
  dst.dword[i] = (i % 2 == 1) ? a.dword[i / 2] : b.dword[i / 2];
}
for (; i < 4; i++) {
  dst.dword[i] = (i % 2 == 1) ? a.dword[i / 2 + 1] : b.dword[i / 2 + 1];
}

// Expands to:

if (0) {
  dst.dword[0] = b.dword[0];
  dst.dword[1] = a.dword[0];
  dst.dword[2] = b.dword[2];
  dst.dword[3] = a.dword[2];
}

Tested on real machine.

Latency and Throughput

CPU	µarch	Latency	Throughput (IPC)
3C5000	LA464	1	2
3A6000	LA664	1	4
3C6000	LA664	1	4

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All intrinsics in alphabetical order