__lasx_xvssrarni_h_w

LASX intrinsic · group: Shift

Synopsis

__m256i __lasx_xvssrarni_h_w (__m256i a, __m256i b, imm0_31 imm)
#include <lasxintrin.h>
Instruction: xvssrarni.h.w xr, xr, imm
CPU Flags: LASX

Description

Arithmetic right shift with rounding the signed 32-bit elements in a and b by imm, saturate the result to signed 16-bit, write the 16-bit result into the lower half of each 128-bit lane of dst, and zero the upper half.

Operation

for (int i = 0; i < 8; i++) {
  if (i < 4) {
    s32 temp;
    if (imm == 0) {
      temp = (s32)b.word[i];
    } else {
      temp = ((s32)b.word[i] >> imm) + (((s32)b.word[i] >> (imm - 1)) & 1);
    }
    dst.half[i] = clamp<s32>(temp, -32768, 32767);
  } else {
    s32 temp;
    if (imm == 0) {
      temp = (s32)a.word[i - 4];
    } else {
      temp =
          ((s32)a.word[i - 4] >> imm) + (((s32)a.word[i - 4] >> (imm - 1)) & 1);
    }
    dst.half[i] = clamp<s32>(temp, -32768, 32767);
  }
}
for (int i = 8; i < 16; i++) {
  if (i < 12) {
    s32 temp;
    if (imm == 0) {
      temp = (s32)b.word[i - 4];
    } else {
      temp =
          ((s32)b.word[i - 4] >> imm) + (((s32)b.word[i - 4] >> (imm - 1)) & 1);
    }
    dst.half[i] = clamp<s32>(temp, -32768, 32767);
  } else {
    s32 temp;
    if (imm == 0) {
      temp = (s32)a.word[i - 8];
    } else {
      temp =
          ((s32)a.word[i - 8] >> imm) + (((s32)a.word[i - 8] >> (imm - 1)) & 1);
    }
    dst.half[i] = clamp<s32>(temp, -32768, 32767);
  }
}

Tested on real machine.

Latency and Throughput

CPU	µarch	Latency	Throughput (IPC)
3C5000	LA464	4	1
3A6000	LA664	4	2
3C6000	LA664	4	2

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