__lsx_vilvl_d
LSX intrinsic · group: Misc
Synopsis
__m128i __lsx_vilvl_d (__m128i a, __m128i b)
#include <lsxintrin.h>
Instruction: vilvl.d vr, vr, vr
CPU Flags: LSX
Description
For each 128-bit lane, interleave the 64-bit elements in the lower half of that lane from a and b: the element from b is placed at the even output position and the element from a at the following odd position.
Operation
for (int i = 0; i < 2; i++) {
dst.dword[i] = (i % 2 == 1) ? a.dword[i / 2] : b.dword[i / 2];
}
// Expands to:
if (0) {
dst.dword[0] = b.dword[0];
dst.dword[1] = a.dword[0];
}
Tested on real machine.
Latency and Throughput
| CPU | µarch | Latency | Throughput (IPC) |
|---|---|---|---|
| 3C5000 | LA464 | 1 | 2 |
| 3A6000 | LA664 | 1 | 4 |
| 3C6000 | LA664 | 1 | 4 |
| 2K1000LA | LA264 | 1 | 1 |
| 2K3000 | LA364E | 1 | 1 |