x86srl.d
LBT intrinsic · group: x86 Shift
Synopsis
Instruction: x86srl.d rj, rk
CPU Flags: LBT
Description
x86-style shift right logical: shift 64-bit value in rj right logically by the amount specified in rk. If shift count is non-zero, update CF, PF, ZF, SF (and OF if count is 1). If shift count is zero, flags are unchanged. Only EFLAGS (LBT4) is updated; the GPR is not modified.
Operation
uint64_t v = (uint64_t)a;
unsigned c = (unsigned)(b & 0x3f);
if (c != 0) {
uint8_t carry_out = c > 64 ? 0 : ((v >> (c - 1)) & 1);
uint64_t r = c >= 64 ? 0 : (v >> c);
EFLAGS.CF = carry_out;
EFLAGS.PF = parity_even((uint8_t)r);
EFLAGS.ZF = r == 0;
EFLAGS.SF = (int64_t)r < 0;
if (c == 1) {
EFLAGS.OF = ((v ^ r) & 0x8000000000000000ULL) != 0;
}
}
Tested on real machine.
Latency and Throughput
| CPU | µarch | Latency | Throughput (IPC) |
|---|---|---|---|
| 3C5000 | LA464 | 2 | 0.5(1/2) |
| 3C6000 | LA664 | 2 | 0.5(1/2) |