x86srli.h
LBT intrinsic · group: x86 Shift
Synopsis
Instruction: x86srli.h rj, imm
CPU Flags: LBT
Description
x86-style shift right logical: shift 16-bit value in rj right logically by immediate imm. If shift count is non-zero, update CF, PF, ZF, SF (and OF if count is 1). If shift count is zero, flags are unchanged. Only EFLAGS (LBT4) is updated; the GPR is not modified.
Operation
uint16_t v = (uint16_t)a;
unsigned c = (unsigned)imm;
if (c != 0) {
uint8_t carry_out = c > 16 ? 0 : ((v >> (c - 1)) & 1);
uint16_t r = c >= 16 ? 0 : (v >> c);
EFLAGS.CF = carry_out;
EFLAGS.PF = parity_even((uint8_t)r);
EFLAGS.ZF = r == 0;
EFLAGS.SF = (int16_t)r < 0;
if (c == 1) {
EFLAGS.OF = ((v ^ r) & 0x8000) != 0;
}
}
Tested on real machine.
Latency and Throughput
| CPU | µarch | Latency | Throughput (IPC) |
|---|---|---|---|
| 3C5000 | LA464 | 2 | 0.5(1/2) |
| 3C6000 | LA664 | 2 | 0.5(1/2) |